The need for low power and high-speed ADC pushes for dynamic comparators to reduce power consumption and maximize speed. This paper presents an analysis of delay, speed, and comparator considerations, and analytical expressions are derived. Using the equation expression More
The need for low power and high-speed ADC pushes for dynamic comparators to reduce power consumption and maximize speed. This paper presents an analysis of delay, speed, and comparator considerations, and analytical expressions are derived. Using the equation expressions, we can understand the design of comparators and make trade-offs. Based on the presented analysis, a new dynamic comparator is proposed by modifying the circuit of the conventional tail comparator for high speed and low power at small supply voltages without complicating the circuit design, resulting in a remarkable reduction in delay time and incremental speed. Simulation results in a 180 nm CMOS technology confirm the analysis results. It is shown that the proposed conventional tail comparator reduces power consumption and increases speed. The simulation results show that the proposed comparator operates up to 2.5GHz with a delay of 69ps and consumes only 329 μW at a supply voltage of 1.2 V and an offset standard deviation of 7.8 mW.
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